1. Field of Invention
The present invention relates to forward converters and more particularly to forward DC/DC converters with adjustable resets.
2. Description of Related Art
FIG. 1 illustrates an existing forward converter design with resonant reset. Converters typically have a primary and a secondary circuit. The primary circuit includes a MOSFET QPR, having a resonant reset capacitor Cr, where MOSFET QPR is coupled to a terminal of the primary coil of Power Transformer T1. The other terminal of the primary coil is driven by a DC voltage source Vin. The secondary circuit includes MOSFETs QFR and QFW, and inductor L1.
A function of MOSFET QPR is to control the energy transfer from DC source Vin to load R_L. In the secondary circuit MOSFETs QFR and QFW constitute a control driven synchronous rectification stage. Here the term “control driven” indicates a forced commutation of MOSFETs QFR and QFW, based on the signals generated by the control circuit of the converter. The control circuit includes Control Block U1, controlling the gates of MOSFETs QPR, QFR, and QFW through corresponding gate drivers U2, U3, and U4, respectively. The MOSFETs QPR, QFR, and QFW contain, as a byproduct of the manufacturing process, a parasitic rectifier, or body diode, which can be thought of as a diode connected across the MOSFET channel, as shown explicitly in FIG. 1.
FIG. 2 illustrates the timing diagrams of the forward converter of FIG. 1. The forward converter exhibits resonant reset and synchronous rectification and operates as follows. When MOSFET QPR is ON, energy transfers from the primary side of Power Transformer T1 to the secondary side. In the timing diagram G_QPR, G_QFR and G_QFW are the gate voltages of MOSFETs QPR, QFR, and QFW, respectively. V_A, V_B, and V_C indicate voltages at points, or terminals, A, B, and C, respectively.
When MOSFET QPR is ON, MOSFET QFR is also ON and MOSFET QFW is OFF. In FIG. 2 this is indicated by G_QPR and G_QFR being “High” and G_QFW being “Low”. When MOSFET QPR is ON, voltages V_B and V_C are essentially zero.
When MOSFET QPR turns OFF, V_C increases very fast, until resonant capacitor Cr charges to a voltage essentially equal to Vin. Once Cr charged to the Vin level, the time dependence of V_C is determined by the resonant dynamics of the LC circuit formed by the primary coil with inductance Lpr and resonant capacitor Cr. V_C increases and decreases in a resonant manner as shown by the timing diagram in FIG. 2.
V_C cannot drop below Vin while MOSFET QPR is OFF. Therefore, when during the resonant cycle V_C drops back to the Vin value, it stays level until the beginning of a new cycle. The time interval, when V_C remains constant is denoted by tDT and is referred to as Dwell Time, as indicated in FIG. 2.
The magnetizing current Im, which flows through the primary coil of Power Transformer T1, increases during the time when MOSFET QPR is ON, governed by:
  Im  =                    V        IN            *              t        ON                    L      PR      
where LPR is the inductance of the primary coil of Power Transformer T1 and tON is the time, when MOSFET QPR is ON.
The value of magnetizing current Im, decreases and reaches zero when V_C reaches its peak. Im continues to decrease to negative values until V_C drops back to the Vin level after half of the resonant cycle passed. After this moment, V_C stays at the Vin level for the tDT interval. Accordingly, Im does not change either in the tDT interval. In this interval Im is negative and flows through the parasitic rectifier of MOSFET QFR. At this time V_C can not drop below Vin level, because the body diode of MOSFET QFR (that is OFF at this time) is forward biased, essentially clamping V_C to the Vin level.
When MOSFET QPR is ON, the secondary-side current through the load is denoted by I_L, which is then reflected back to the primary side as I_LR:
  I_LR  =      I_L    N  
The total current through the primary coil is the sum of the magnetizing current Im and the reflected current I_LR:I—QPR=Im+I—LR 
as shown in FIG. 2.
In an analogous manner, the Im magnetizing current of the primary circuit generates an Im_R reflected magnetizing current in the secondary circuit:Im—R=Im*N 
The total current in the secondary circuit is the sum of the reflected magnetizing current Im_R and the load current I_L.
Losses, which occur during the Dwell Time tDT, decrease the efficiency of the converter. The Dwell Time loss PDT is:
  PDT  =            Vfd      *      Im_R      *              t        DT              T  
where T is a switching period and Vfd is the forward voltage drop across the parasitic diodes of MOSFET QFR. A typical value for Vfd is in the range of about 0.5V to about 1V, depending on the type of MOSFETs. In some MOSFETs Vfd is about 0.7 V.
Losses during the Dwell Time are often so large that they significantly reduce the overall efficiency of the converter.
A method to reduce Dwell Time losses was described in: “The Implication of Synchronous Rectifiers to the Design of Isolated, Single-Ended Forward Converters”, by Christopher Bridge, (Unitrode Products from Texas Instruments, Power Supply Design Seminar, 2001).
FIG. 3 illustrates a block-diagram of the suggested system. In this system MOSFETs QFR and QFW are turned ON and OFF with some delay. These delays are adjusted based on the various MOSFET voltages as described below.
FIG. 4 illustrates the timing diagram of the system of FIG. 3. Quantities are labeled analogously as in FIG. 2. The timing traces of several quantities in FIG. 4 are very similar to those of FIG. 2.
A difference from FIG. 2 is that MOSFET QFR is turned ON at the beginning of the Dwell Time. Therefore, during Dwell Time both MOSFETs QFR and QFW are ON. When MOSFET QPR turns ON, MOSFET QFR stays ON. When MOSFET QPR turns OFF, MOSFET QFR turns OFF and MOSFET QFW turns ON and the cycle repeats.
This system has an improved efficiency because the reflected load current during the Dwell Time does not flow through the parasitic diode of MOSFET QFR, but through its main channel, as QFR is turned ON. Since the resistance of the main channel is negligible compared to that of the parasitic diode, the losses during Dwell Time are reduced considerably.
FIGS. 5 A–B illustrate an additional aspect of these converters. The term “commuting” is used to describe the sequence of switching of various MOSFET voltages. In a MOSFET it takes a finite time to fully reach a new voltage after the switching started. This is why the voltages in FIGS. 5A–B rise and fall with a finite slope.
FIG. 5A illustrates a non-optimal commutation of voltages in MOSFET QFW. V_A, the voltage at terminal A, drops towards zero, when MOSFET QPR turns OFF. Essentially simultaneously, the polarity across inductor L1 changes because inductor L1 tries to maintain its current. This causes V_A to drop past zero to negative values. However, because MOSFET QFW is OFF, V_A drops negative not more than one diode voltage drop, because the body diode of MOSFET QFW is forward biased. Voltage Vds across MOSFET QFW drops to zero and goes negative in a way analogous to V_A.
After a time interval D the gate voltage Vgs of MOSFET QFW rises, eventually turning ON. During the intermediate time interval D the current is forced to flow through the parasitic diode of the MOSFET, leading to high dissipative losses.
FIG. 5B illustrates an optimized commutation of MOSFET QFW. Here Vgs rises before Vds drops to zero. Therefore, MOSFET QFW is turned ON before Vds drops to zero, and the current is not forced through the parasitic diode. Therefore, this commutation avoids the high dissipation.
Returning to FIG. 3, it is illustrated that the suggested system employs a Control Block U1 to control the turning of MOSFETs QFR and QFW trough adjustable Turn ON/OFF Delay circuits. Control Block U1 functions in accordance with the voltage levels of the MOSFETs. Control Block U1 optimizes the commutation timing of the MOSFETs QFR and QFW as described in relation to FIG. 5B, reducing converter switching losses. Other related circuits were suggested in U.S. Pat. Nos. 6,001,703, 6,026,005, and 6,188,592, incorporated herein in their entirety by reference.